1. Field of the Invention
The present invention relates to a floppy disk apparatus including a stepping motor.
2. Description of the Related Art
In recent years, floppy disk apparatuses that use a USB (Universal Serial Bus) interface instead of the conventional legacy interface as the interface with the host apparatus, such as a personal computer, have become available as commercial products. Such known floppy disk apparatuses are disclosed in, for example, Laid-open Japanese Patent Application No. H. 11-306501 and Laid-open Japanese Patent Application No. 2000-311422. The basic configuration of the known floppy disk apparatuses is as shown in FIG. 3. Specifically, such a floppy disk apparatus 101 includes an interface control circuit 110 that communicates with the host apparatus 2 through a USB, a floppy disk control circuit 111 that receives a control signal, control data or write data from an interface control circuit 110 or sends read data to the interface control circuit 110 and that controls a spindle motor drive circuit 12, a stepping motor drive circuit 14 and a read/write circuit 16 (described subsequently), a spindle motor drive circuit 12 that is controlled by the floppy disk control circuit 111, a spindle motor 13 that is driven by the spindle motor drive circuit 12 so as to rotate the floppy disk, a stepping motor drive circuit 14 that is controlled by the floppy disk control circuit 11, a stepping motor 15 that shifts a magnetic head (described subsequently), driven by the stepping motor drive circuit 14, a read/write circuit 16 that performs input/output of read and write data with the floppy disk control circuit 111 and performs input/output of electrical signals with respect to the magnetic head, and a magnetic head 17 that converts magnetic signals on the floppy disk to electrical signals and converts electrical signals to magnetic signals.
The function of the floppy disk drive controller (FDC), provided in the host apparatus in a conventional legacy interface (such as, for example Laid-open Japanese Patent Application No. H. 9-261997), is incorporated in the interface control circuit 110 in the USB interface floppy disk apparatus 101. Consequently, signals like those of the legacy interface are used between the interface control circuit 110 and the floppy disk control circuit 111.
FIG. 4 shows a circuit block diagram relating to drive and control of a stepping motor 15 used in the floppy disk apparatus 101. The interface control circuit 110 outputs a first step pulse signal STP that constitutes the reference for the rotational speed of the stepping motor 15 and a direction signal DIR that determines the direction of rotation, in accordance with an instruction from the host apparatus 2 (not shown in FIG. 4). The floppy disk control circuit 111 inputs these signals and generates and outputs control signals a+, a− and b+, b− that control the stepping motor drive circuit 14. Specifically, the floppy disk control circuit 111 includes a step pulse period detection circuit 111D that detects the period T of the first step pulse signal STP, a second pulse generating circuit 111S that generates a second step pulse signal STP2 from the output signal of the step pulse period detection circuit 111D and the first step pulse signal STP, and a control signal generating circuit 111C that generates the control signals a+, a− and b+, b− from the first step pulse signal STP, second step pulse signal STP2 and direction signal DIR.
Next, control of the stepping motor 15 will be described with reference to FIG. 5, which is a waveform diagram of the various signals described above. The first step pulse signal STP has a pulse in the negative direction having a period T that is changed in accordance with an instruction from the host apparatus 2 and is, for example, 5 mS. The second step pulse signal STP2 has a pulse in the negative direction that falls with a delay of a predetermined time after the fall of the first step pulse signal STP. The delay time to of the initial second step pulse signal STP2 is determined under a condition in which the period T of the first step pulse signal STP is not detected and is therefore set to about 1.5 mS, corresponding to the minimum period T of the first step pulse signal STP that can be instructed by the host apparatus 2, to enable rotation of the stepping motor 15. The delay time t1 of the second step pulse signal STP 2 on the second and subsequent occasions is generated directly in response to detection of the period T of the first step pulse signal STP and is ½ of the period T of the first step pulse signal STP (e.g., about 2.5 mS). If the direction signal DIR is low level that indicates the forward rotation, control signals a+, a− that toggle (repeatedly invert on each pulse) in synchronization with the first step pulse signal STP are generated and control signals b+, b− that toggle in synchronization with the second step pulse signal STP2 are generated. It should be noted that when rotation is effected in the reverse direction, control signals b+, b− are generated in synchronization with the first step pulse signal STP and control signals a+, a− are generated in synchronization with the second step pulse signal STP2.
Thus, since the second and subsequent second step pulse signals STP2 are generated after detection of the period T of the first step pulse signal STP, the delay time t1 is adequate, in accordance with the period T. An adequate delay time is about ½ of the period T so as to achieve smooth rotation of the stepping motor 15. In contrast, since the period T of the initial first step pulse signal STP at which rotation of the stepping motor 15 is commenced cannot be detected, the initial second step pulse signal STP2 is selected to have a delay time to of about 1.5 mS, corresponding to the minimum of the period T of the first step pulse signal STP that can be instructed by the host apparatus 2 to produce some rotation of the stepping motor 15, whatever the period T, even if this rotation is not smooth. Therefore, at this time, power efficiency is lowered and noise is generated since the delay time is inadequate.